Square root device employing converging approximations



Feb. 3, 1966 L ROTH ETAL 3,234,369

SQUARE ROOT DEVICE EMPLOYING CONVERGING APPROXIMATIONS Filei Dec. 136, 1961 4 l6 Sheets-Sheet 1 2 2 RADICAND 25 2 ()1 kzov -20 19 FIG, 1 1+ SQUARE ROOT (D l COMPUTER ADDEND 1 a I FIG. FIG. 0 I 51 1a 1b ADDEND 2] I 36 Ii 5 A112 SUM g l i (3 6M9 7 22 21 26 23 22 21 2O 1 @0 $2 J I 54 $662 ADDEND 1 8T7 I: Y: 1 I32 I ?QJ 492 ADDEND 2 I l 56 0 Q I I I SUM E? 5 5' 5' i i 1 o o 0 1 54 I *\-T -W k- 1M l 1 a I 1 1. I g I I l l x40 I l t l I L .l

Fl G 1Q INVENTORS ROBERT 1. ROTH HAROLD FLEISHER 3 2 2 SQUARE ROOT 2 ATTORNEY Feb. 8, 1966 R. 5. HOTH ETAL.

SQUARE ROOT DEVICE EMPLOYING CONVERGING APPROXIMATIONS l6 Sheets-Sheet L Filed Dec. 13, 1961 CRYOTRONS FIG FIG FIG FIG FIG FIG Feb. 8, 1966 R. l. ROTH ETAL 3,234,369

SQUARE ROOT DEVICE; EMPLOYING CONVERGING APPROXIMATIONS Filed Dec. 13, 1961 16 Sheets-Sheet 6 00 J 00 X 01 X ()1 i 0 /3 f Mi 8, 1966 R. I. Rm-H Em. 3,2343% DYING CONVERGING APPROXIMATIONS SQUARE RQOT DEVICE EMPL- 16 Sheets-Sheet 7 Filed Dec. 13, 1961 Feb. 8, 1966 R. I. ROTH ETAL SQUARE ROOT DEVICE EMPLOYING CONVERGING APPROXIMATIONS l6 Sheets-Sheet 10 Filed Dec. 13, 1961 SELECTOR CRYOGENIC EMBODIMENT ENPUT FE G.

DiSTRIBUTOR CRYOGENIC EMBODIMENT 16 Sheets-Sheet 11 R. ROTH ETAL 2 ADDEND 1- 2 SQUARE ROOT DEVICE EMPLOYING CONVERGING APPROXIMATIONS Feb. 8, 1966 Filed Dec. 13, 1961 ADDFEND 2 FIG 60 ADDER NEON- PC EMBODIMENT Feb. 8, 1966 R. 1. ROTH ETAL SQUARE ROOT DEVICE EMPLOYING CONVERGING APPROXIMATIONS l6 Sheets-Sheet 12 Filed Dec. 13, 1961 FIG. 6b

Feb. 8, 1966 R. ROTH ETAL 3,234,369

SQUARE ROOT DEVICE EMPLOYING CONVERGING APPROXIMATIONS Filed Dec 13, 1961 16 Sheets-Sheet 1'5 NEON LAMPS Feb. 8, 1966 R. l. ROTH ETAL SQUARE ROOT DEVICE EMPLOYING CONVERGING APPROXIMATIONS l6 Sheets-Sheet 14 Filed Dec. 15, 1961 FIG. 7b

1| .4 4 l ll l oa ox ol o .1 111 11001 141 :11

Feb. 8, 1966 R ROTH ETAL 3,234,369

SQUARE ROOT DEVICE EMPLOYING CONVERGING APPROXIMATIONS Filed Dec. 13, 1961 16 Sheets-Sheet l5 Feb. 8, 1966 SQUARE ROOT DEVICE EMPLOYING CONVERGING APPROXIMATIONS Filed Dec 13, 1961 R. I. ROTH ETAL 3,234,369

16 Sheets-Sheet 16 FIG. 8

SELECTOR NEON- PC EMBODIMENT SELECT A? INEUT A O A I 2 H j i 176 176 OUTPUT INPUT B United States Patent 3,234,369 SQUARE ROOT DEVICE EMPLOYING CON- VERGING APPROXIMATIONS Robert I. Roth, Briarclifi Manor, and Harold Fleisher,

Poughkeepsie, N.Y., assignors to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Dec. 13, 1961, Ser. No. 159,034 8 Claims. (Cl. 235164) This invention relates to computing techniques and, in particular, to computing techniques for solving those problems which lend themselves to resolution by iterative processes of converging approximations. Included in this class of problems are root determinations, division, problems which may be resolved by techniques employing continued fractions, and many others.

Many computers that are adaptable for use in solving problems of the type defined above utilize shift registers and other circuits requiring synchronization. These computers inherently require control circuits and are beset with complex timing problems. The present invention involves computing techniques that avoid these and other difficul'ties that are inherent in many prior art devices. In the present invention, completely unsynchronized apparatus is used to provide a solution to problems of the class outlined above. In addition, these techniques provide a continuous solution which is promptly corrected when the computer input data is changed.

These computing techniques are shown in two embodiments of square root computers, one utilizing cryogenic elements and the other neon lamps and \photoconductor elements. These embodiments are especially useful in illustrating the invention because the derivation of square roots is known to pose relatively complex problems.

An object of the present invention is to demonstrate computing techniques that do not require synchronization.

Another object is to teach computing techniques for solving problems which lend themselves to resolution by iterative processes of converging approximations.

A more particular object of the present invention is to show an unsynchronized square root computer.

A futher object is to show an unsynchronized, digital square root computer using cryogenic elements.

Another object is to show an unsynchronized, digital square root computer using neon-photoconductor elements.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawrugs.

The unsynchronized computing techniques of the present invention are embodied in square root computers. Among the available techniques for computing square roots is the iterative method that is often used in paper and pencil calculations and which is illustrated in the following example for extracting the square root of the decimal radicand 81,796:

Step 1.Partition the radicand into pairs of digits, counting from the decimal point.

3,234,369 Patented Feb. 8, 1966 Step 2.Select, as the highest order digit of the square root, the largest number (2) whose square does not exceed the value of the highest order radicand pair (08).

Step 3.Subtract the square (4) of the number (2) selected in step two from the highest order radioand pair (08) and place the next pair of radicand digits (17) to the right of this difference (to obtain 417).

Step 4.Select, as the next digit of the square root, the largest number (8) which does not generate a product (384) that exceeds the number (417) determined in step three when multiplied by a number (48) obtained by doubling the digit (2) obtained in step two followed by the number (8) selected in this step.

Step. 5.Subtract the product (384) referred to in step four from the number (417) obtained in step 3 and place the next pair of radicand digits (96) to the right of this difference (to obtain 3396).

Step 6.Repeat ste four, operating on the number (3396) obtained in step five.

This same procedure may be used for determining square roots of numbers in other radices and the following example illustrates the extraction of the square root of the binary radicand 10101001:

The procedure is considerably simpler in the binary system than in the decimal system because a number is doubled merely by placing a zero to its right. For example, the binary number 11 is doubled by adding a zero to obtain 110. Furthermore, since numbers in the binary system are limited to either 0 or 1, the relatively complicated selections made in steps four and six in the decimal example above degenerate into a determination of Whether a number comprised of the previously-determined radicand digits, followed by the digits 01, (corresponding to doubling the previouslydetermined radicand digits and tentatively selecting a 1 as the next radicand digit), exceeds the result of the previous subtraction (steps three and five). In the present invention, this procedure is modified to replace the subtraction operations with addition and an example of this modified procedure for extracting the square root of the binary radicand 10101001 (used in the above example) fellows:

Ste J.-Generate the complement of the radicand by replacing each with a 0 and each 0 with a l and then partition the complemented radicand into pairs of digits, starting from the binary point.

Step 2.Add, to the first pair of complemented radicand digits (01), the square of (1) of the largest number (1) which doe-s not generate a 1 carry. This number -(1) represents the highest order digit of the uncomplemented square root.

Step 3.Plac,e the next pair of complemented radicand digits (01) to the right of the sum (10) generated in step two (to obtain 1001).

Step 4.-Select, as the next digit (1) of the square root, the largest number (1) which, when multiplied by twice the previously generated square root digit (1) followed by the selected number, does not result in a 1 carry when added to the number (1001) obtained in step three. Add this product to the number obtained in step three. This may be done mechanically by tentatively adding 01 to the right of the previously generated square root digits and checking for a carry when adding to the number obtained in step three. As stated above, adding 01 to the right of a binary number corresponds to doubling the number and tentatively selecting a l as the next radicand digit. If a carry is generated, this indicates that a could have been selected and, in this case, the result of tentative addition is not used and the number obtained in step three is carried down and the next two digits of the complemented radicand are placed to the right of this number.

Steps 8.-Rep-eat steps three and tour alternately to generate the remainder of the digits of the square root. When a sum made up of all 1 bits with a 0 carry is obtained, the exact square root has been extracted.

The procedure outlined in the last example is readily adaptable to unsynchronized computer circuitry and forms the basis of operation of the computers embodying the invention as shown in the accompanying drawlllgS.

In the drawings:

FIGURE 1 is an organizational diagram illustrating the interconnection otE FIGURES la and 1b.

FIGURES 1a and 1b comprise a block diagram of a square root cumputer.

FIGURE 2 is a detailed diagram of an adder circuit suitable for use in a cryogenic embodiment of the invention shown in FIGURE 1.

7 FIGURE 3 is an organizational diagram illustrating the interconnection of FIGURES 3a.3f.

FIGURES Zia-3f comprise a chart indicating the status of the cryogenic elements in the adder shown in FIG- URE 2 for all possible addend inputs.

FIGURE 4 is a detailed diagram of a selector circuit "suitable for use in a cryogenic embodiment of the invention in FIGURE 1.

FIGURE 5 is a detailed diagram of a distributor circuit suitable for use in a cryogenic embodment of the invention shown in FIGURE 1.

FIGURE 6 is an organizational diagram illustrating the interconnection of FIGURES 6a and 6b.

FIGURES 6a and 6b comprise a detailed diagram of an adder circuit suitable for use in a neon-photoconductor embodiment of the invention shown in FIGURE 1.

FIGURE 7 is an organizational diagram illustrating the interconnection of FIGURES 7a-7c.

FIGURES 7a-7c comprise a chart indicating the status of the neon lamps in the adder shown in FIGURE 6 for all possible addends.

FIGURE 8 is a detailed diagram of a selector circuit suitable for use in a neon-photoconductor embodiment of the invent-ion shown in FIGURE 1.

Many of the numbers in the block diagram in FIG- URE 1 are encircled. These circles may be ignored during the following general description as they relate to an illustrative example which follows the general description.

An eight-bit (digit) radicand is applied to the input of the square root computer shown in FIGURE 1 on leads 20. Each pair of leads corresponds to one bit of data. The pairs of leads are also labelled to indicate the radicand bit orders (2 through 2").

The lowest two orders (2 and 2 of the radicand are applied as part of a first input (addend 1) to an adder 22. The next higher two orders of the radicand input are similarly applied to another adder 24, and the successively higher orders of the radicand are applied to adders 26 and 28. The radicand is automatically complemented as applied to the adders by applying each 1 lead as the 0 data and each 0 lead as the 1 data of the corresponding adder position or order. Each adder contributes one bit of data to the output square root on a pair of leads 30. These pairs of leads are also labelled to correspond to the order of the output (2 through 2 The two lowest-order bits of the second input (addend 2) to each adder are 01 and this is accomplished by connecting the appropriate adder inputs to a fixed signal applied through leads 32. This operation corresponds to doubling the higher-order bits and tentatively selecting a l for each bit of the square root. The remaining (higher-order) bits to the second input (addend 2) of each adder (except the highest order adder 28) represent the bits of the square root generated by the higherorder adders. Each adder generates a tentative sum including a carry bit as the highest order bit of the sum. As described above with respect to the last sample calculation, each bit of the square root is selected as the largest number that provides no carry. Thus, a 1 carry indicates that the tentatively selected bit (1) is too large and that a 0 should have been selected. Therefore, each bit of the square root is merely the complement of the carry signal generated in the appropriate adder. This complementing operation is accomplished by properly labelling the square root output leads. Since a 0 carry indicates that the corresponding bit of the square root is a 1 and that the result of the tentative addition should be used, this 0 signal is applied to condition an and gate 34 which passes the sum to the subsequent (lower-order) adder where it forms the higherorder bits of one input. The two lower-order bits of this adder input are the subsequent (lower-order) pair of complemented radicand bits, as described above. Similarly, a 1 carry indicates that the corresponding bit of the square root is a 0 and that the result of the tentative addition should not be used. In this case, the "1 carry signal is applied to condition an an gate 36 which passes the first adder input (addend 1) rather than the sum to the subsequent (lower order) adder.

In FIGURE 1, each pair of and gates 34, 36 is considered to form a selector 38 and the distribution network for each carry signal is considered to form a distributor 40. This combination of and gates and networks into selectors and distributors has been done mere- 1y to facilitate the detailed discussion of these circuits.

The following description of the step-by-s-tep operation of the system shown in FIGURE 1 for the radicand 10101001 (also used in the introductory examples) is included to provide a better understaanding of the invention.

The sample input radicand 10101001 on leads 20 is shown in FIGURE 1 by the encircled 0 and 1 lead designations. This number is complemented by the connections to the adder as indicated by the encircled addend data. Thus, the highest order radicand bits 10 are complemented into 01 as applied to adder 28. The second input to this adder corresponds to "01 because of the fixed connections, and a sum of 10 with a 0 carry is generated. This 0 carry indicates that the highest-order bit of the square root bit is a l (as indicated). The 0 carry is also applied to condition an and gate 34 which supplies the sum 10 from adder 28 to the higher bit positions of the first input of the subsequent adder 26. The lower order bits of this input are 01 representing the complement of the appropriate radicand bits. The 0 carry output of adder 28 (corresponding to a square root output bit equal to l) is directly applied as the highest-order bit of the second input to adder 26. The two lower-order bits of this input are 01 from the fixed connections. Adder 26 generates a sum 1110 with a "0 carry as indicated by the encircled notations. The 0 carry indicates that the second-highcst-order bit of the square root is also a 1. In a similar manner, the sum generated by adder 26 is supplied as the higher-order bits of the first input to adder 2 4, and the appropriate complemented radicand bits are used as the lower-order entries. The lower-order bits of the second input to the adder 24 are 01 because of the fixed connections and the previously generated radicand bits 11" are used as the higher-order entries. Adder 24 generates a sum of 0001- with a I carry. This indicates that the corresponding square root bit is a 0 and that the generated sum is not to be applied to the subsequent adder. In this case, the 1 carry conditions and gate 36 which passes the first input of adder 24 to the higher-order positions of the first input of the lowest-order adder 22. This generates a sum of 11111111 and a O carry, indicating that the final (lowest-order) bit of the square root is 1 and that the root has been exactly determined.

The computer shown in block diagram of FIGURE 1 has been shown to generate the square root of the applied radicand according to the technique shown in the introductory examples. This computer requires no synchro nization and fluctuations in the input radicand are continuously reflected in the generated square root.

The adders, selectors, and distributors shown in FIG- URE 1 will now he described in detail with respect to a cryogenic embodiment and a neon-photoconductor embodirnent.

A typical cryogenic adder of the type that may be used in this invention is shown in FIGURE 2. This adder accepts a four-bit addend, labelled addend 1, applied on leads 50, and a three-bit addend, labelled addend 2, applied on leads 52, and generates a five-bit sum on leads 54, where the highest-order bit of the sum is considered to be the carry bit referred to in the description with respect to the block diagram of FIGURE 1. This adder can obviously be modified to provide any desired bit capacity.

The adder shown in FIGURE 2 utilizes cryogenic elements which are called cryotrons. The cryotrons used in the present invention are devices having two current paths: an input or contro path and an output or 'gate" path. In operation, a current flows in the gate (output) path when no current is applied to the control (input) path. Thus, a cryotron may be considered as a logical inhibitor element. In FIGURE 2, each cryotron is shown :by a rectangle with the gate current flowing in the leads connected to its ends and the control current flowing in the leads connected to its sides.

The lowest-order (2) addend input bits are applied to a group 56 of four cryotrons. The addend 2 bit supplies the control current to the cryotrons and, in conjunction with the addend 1 bit, determines the 2 sum.

When the 2 addend 1 bit is 0, current flows in the path toward cryotrons 56-1 and 56-2 and the 2 addend 2 bit provides the control current to determine which of these two cryotrons has a gate current. When the 2 addend 2" bit is 0, cryotron 56-1 is inhibited and current flows through cryotron 56-2 to provide a 0 as the 2 sum bit. When the 2 addend 2 bit is 1 (and the 2 addend 1 bit remains 0), cryotron 56-2 is inhibited and current flows through cryotron 56-1 to provide a "1" as the 2 sum bit. Similarly, a 2 addend 1 bit of 1 and a 2 addend 2 bit of 0 generates a 1 as the 2 sum bit by current flow through cryotron 56-4. When both 2 addend bits are l, cryotron 56-3 passes current to provide a 2 sum bit of 0. 1 he current flowing from the group 56 of cryotrons is also used to control another group 58 of cryotrons which provide a carry signal when both 2 addend bits are 1, as will be described below.

The 2 addend bits are similarly applied to a group 60 of cryotrons whose operation is similar to the operation of group 56, but the out-put current from this group is further controlled by a. group 62 of cryotrons before the 2 sum bit is determined. This group 62, in conjunction with group 5 8, modify the 2 sum bit to account for a 2 carry bit of 1 when both 2 addend bits are 1. In this case, cryotron 58-1 is inhibited and current flows through cryotrons 58-2 and 58-3 to inhibit cryotrons 62-1, 62-2 and 62-3, and uninhibited cryotrons 62-4, 62-5 and 62-6 have the efi'ect of inverting the otherwise present 2 sum output. When a 2 carry of 0 is indicated (by gate current flow through cryotron 58-1), cryotrons 62-4, 62-5 and 62-6 are inhibited and uninhibited cryotrons 62-1, 62-2 and 62-3 pass the output of group 60 without alteration as the 2 sum bit.

Similarly, groups 64 through 7 6 of cryotrons control the generation of the higher-order sum bits. The chart in FIGURE 3 indicates the operation of each cryotron in the adder in FIGURE 2 for all possible input addends. An X in this chart indicates that the associated cryotron is inhibited by a control current and a indicates that a gate current is present.

A cryogenic embodiment of a selector circuit is shown in FIGURE 4. This circuit is suitable for use in the computer shown in FIGURE 1 in conjunction with the adder shown in FIGURE 2 and the distributor shown in FIG- URE 5.

One of the two inputs (A and B) that are applied to the selector circuit shown in FIGURE 4 is chosen as the circuit output, where the selection is determined by the control signals: Select A and Select B. Each input is shown to include two bits of data but the circuit may obviously be extended to operate on input data having any number of bits.

Input A is applied to a first cryogenic and gate and input B is applied to a second cryogenic and gate 82. The Select A and Select B signals (corresponding to the carry output signals from the preceding adders shown in FIGURE 1) are also applied to the corresponding and gates 80, 82.

When a Select A current is applied to the circuit shown in FIGURE 4, a gate current flows through cryotron 80-1 or 80-2, depending upon the 2 bit of the A input signal. When this bit is 0, cryotron 80-1 is inhibited and gate current flows through ciyotron 80-2. Similarly, when the 2 bit of A input signal is l, gate current flows through cryotron 80-1. The gate current through cryotrons 80-1 and 80-2 is the control current for cryotrons 80-3 and 80-4. Thus, when the 2 bit of A input signal is 0, cryotron 80-4 is inhibited and gate current flows through cryotron 80-3 to provide a 0 as the 2 bit of the output signal. Similarly, when the 2 bit of the A input signal is 1, gate current flows through cryotron 80-4 to provide a 1 output signal. In the same manner, the Select A control signal passes the 2 bit of the A input signal as the 2 bit of the output signal by the operation of cryotrons 80-5, 80-6, 80-7 and 80-8. Cryotrons 82-3, 82-4, 82-7 and 82-8 in and gate 82 have no effect on the output of and gate 80 when the A input signal is to be selected because there is no current applied to the Select B input and, hence, no current available to inhibit any of these cryotrons.

Similarly, cryotrons 82-1 through 82-8 in and gate 82 operate to choose the B input signal as the output signal when a Select B control signal is applied.

A cryogenic embodiment of a distributor circuit is shown in FIGURE 5. This circiut is suitable for use in the computer shown in FIGURE 1 in conjunction with 7 the adder shown in FIGURE 2 and the selector shown in FIGURE 4. This circuit is used to provide a plurality of separate and identical signals where only one signal is available and is used in a cryogenic system to avoid splitting a current into several paths. In FIGURE the single input signal on leads 84 is applied as a first output signal on leads 86 and as the control signal to cryotrons 3(8) to provide additional similar output signals on leads The detailed cryogenic circuits shown in FIGURES 2, 4 and 5 are typical circuits that may be used in a cryogenic embodiment of the computer shown in FIGURE 1. A second embodiment of this computer using neon-photoconductor elements is based on the block diagram of FIGURE 1 and the detailed diagrams of a typical adder shown in FIGURE 6 and a typical selector shown in FIG- URE 8. A detailed diagram of a distributor circuit is not shown because the physical connections shown in the distributor blocks in FIGURE 1 may be used in the neon-photoconductor embodiment.

In the circuits shown in FIGURES 6 and 8, solid lines are used to indicate electrical connections and. dashed lines are used to indicate light paths. The photoconduc tor elements are indicated by rectangles having electrical connections at their ends and light applied at their sides. The photoconductor elements have a high impedance when no light is applied and a low impedance when light is applied. Thus, these elements act as gates, passing current when conditioned by light.

A typical adder shown in FIGURE 6 operates on a four-bit addend (addend 1) and a three-bit addend (addend 2) to generate a five-bit sum, where the highestorder (2 bit corresponds to the carry signal required in the computer in FIGURE 1. FIGURE 6a should be placed above FIGURE 6b to obtain the composite FIG- URE 6'. This typical adder can obviously be extended to operate on any number of addend bits.

In FIGURE 6, the 2 addend 2 signal is applied to operate a corresponding neon lamp 102 or 104 which conditions the corresponding pair of photoconductor (PC) elements 103-1, 103-2 or 105-1, 105-2. The 2 addend 1 signal is then passed to light one of three lamps 106, 107 and 108. When both 2 addend bits equal 0, current flows through PC element 105-2 to light lamp 108. Similarly, when both 2 addend bits equal 1, current flows through PC element 103-1 to light lamp 106. When one addend bit is 0, and the other is 1, current flows through PC element 103-2 or 105-1 to light lamp 107. In the first two cases (0+0 or 1+1), light is applied from a neon lamp 108 or 106 respectively to condition a PC element 112, which provides a 2 output sum bit of 0. In the third case (0+1 or 1+0), light from lamp 107 conditions a PC element 114, which provides at 2 output bit of l.

The 2 addend bits are applied to a similar circuit comprising neon lamps 116 and 118 and PC elements 120-1, 120-2, 122-1 and 122-2, but the output of this circuit is applied to two groups of PC elements 124 and 126. PC elements 124 are conditioned by light from lamp 106 when both 2 addend bits are 1, indicating a 2 carry of 1. For all other combinations of 2 addend bits (0+0, 0+1 or 1+0), a 2 carry of 0 is present and PC elements 126 are conditioned. In the latter case (2 carry of 0) one of a group of neon lamps 128, 130 and 132 is lighted and a PC element 136 or 138 is conditioned to provide a 2 output sum bit in the manner described for the 2 bit addition. However, when a 2 carry of 1 is indicated, PC elements 124 are operated and have the effect of shifting the position of the lighted lamp. That is with a 2 carry equal to l and with 2 addend bits both equal to 0, lamp 130 is lighted (instead of lamp 132 which is lighted when both 2 bits equal 0 and the 2 carry is 0). Similarly, with a 2 carry equal to 1 and with one 2 addend bit equal to 1 and the other 2 addend bit equal to 0, lamp 128 (instead of lamp 130 in the 0 carry case), is lighted; and with a 2 carry of l and with 2 addend bits that are both 1, lamp 134 (instead of lamp 128 in the 0 carry case) is lighted. Thus, a 2 output sum of 0 is indicated for :1 2 carry of 0' and 2 addend bits that are both 0 or both 1, or for a 2 carry bit of l with one 2- addend bit of 1 and one 2 addend bit of 0.

The operation of the adder shown in FIGURE 6 for all possible addends, is outlined in the chart in FIGURE 7 where a indicates a lighted neon lamp.

This chart should be referred to in conjunction with the dashed-line light paths shown in FIGURE 6 for an indication of the status of the PC elements for any pair of addends.

A selector circuit suitable for use in a neon-photoconductor embodiment of the invention is shown in FIG- URE 8.

One of the two inputs (A and B) that are applied to the selector circuit is chosen as the circuit output, where the selection is determined by the control signals: Select A and Select B. Each input is shown to include two bits of data but the circuit may obviously be extended to operate on input data having any number of bits. Each lead corresponding to input A is applied toa PC element 176 and each lead corresponding to input B is applied to a PC element 178. When a Select A control signal is present, a neon lamp is lighted, conditioning its associate-d PC elements 176 which then pass the input A data as the circuit output. Similarly, when a Select B control signal is applied to light neon lamp 182, PC elements 178 are conditioned and the input B data is passed as the circuit output.

Two embodiments of a square root computer have been shown and described in detail. These embodiments are examples of a computing technique that requires no synchronization. This technique makes use of a group of devices for linearly combining a plurality of signals (such as a group of adders) where a portion of the computer input data is applied as one input to each device and where a second input to each device is responsive to the output of the device which has the next higher order input data applied. This technique provides an output which is continuously responsive to the computer input whether it be constant or changing. This computing technique is especially useful in solving that class of problems which lend themselves to an iterative process of converging approximations, such as problems involving division, square roots, cube roots and high-order roots. Thus, this technique is also ideally suited for operating with continued fractions, such as:

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. A computer for generating an indication of the square root of an nth-order radicand comprising, in combination:

a plurality of m unsynchronized linear combination circuits, each corresponding to an order of the mthorder square root of the radicand and each for generating a first and a second output, where each output is indicative of a function of a linear combination of a plurality of applied multiple-order digit representations and where the first output is also indicative of a function of the corresponding digit of the square root; 

1. A COMPUTER FOR GENERATING AN INDICATION OF THE SQUARE ROOT OF AN NTH-ORDER RADICAND COMPRISING, IN COMBINATION: A PLURALITY OF M UNSYNCHRONIZED LINEAR COMBINATION CIRCUITS, EACH CORRESPONDING TO AN ORDER OF THE MTHORDER SQUARE ROOT OF THE RADICAND AND EACH FOR GENERATING A FIRST AND A SECOND OUTPUT, WHERE EACH OUTPUT IS INDICATIVE OF A FUNCTION OF A LINEAR COMBINATION OF A PLURALITY OF APPLIED MULTIPLE-ORDER DIGIT REPRESENTATIONS AND WHERE THE FIRST OUTPUT IS ASLO INDICATIVE OF A FUNCTION OF THE CORRESPONDING DIGIT OF THE SQUARE ROOT; MEANS FOR ESTABLISHING, AS ONE OF THE PLURALITY OF MULTIPLE-ORDER DIGIT REPRESENTATIONS IN THE MTH-ORDER CIRCUIT, THE NTH-ORDER AND (N-1)-ORDER DIGITS OF THE RADICAND AS THE SECOND-ORDER AND FIRST-ORDER REPRESENTATIONS RESPECTIVELY WHEN N IS AN EVEN NUMBER, AND THE NTH-ORDER DIGIT OF THE RADICAND AS THE FIRSTORDER REPRESENTATION WHEN N IS AN ODD NUMBER; MEANS FOR ESTABLISHING, AS THE FIRST-ORDER AND SECONDORDER DIGIT REPRESENTATIONS OF ONE OF THE PLURALITY OF MULTIPLE-ORDER DIGIT REPRESENTATIONS IN THE SUCCESSIVELY LOWER-ORDER CIRCUITS, THE SUCCESSIVELY LOWERORDER PAIRS OF DIGITS OF THE RADICAND, WHERE THE HIGHER-ORDER DIGIT OF EACH PAIR OF RADICAND DIGITS IS ESTABLISHED AS THE SECOND-ORDER DIGIT REPRESENTATION AND THE LOWER-ORDER DIGIT OF EACH PAIR OF RADICAND DIGITS IS ESTABLISHED AS THE FIRST-ORDER DIGIT REPRESENTATION, IN EACH CIRCUIT; SELECTOR MEANS RESPONSIVE TO THE FIRST OUTPUT OF THE NEXT HIGHER-ORDER CIRCUIT FOR ESTABLISHING, AS THE REMAINING DIGITS OF THE SAID ONE OF THE PLURALITY OF MULTIPLE-ORDER DIGIT REPRESENTATIONS IN EACH CIRCUIT EXCEPT FOR THE CIRCUIT CORRESPONDING TO THE MTHORDER DIGIT OF THE SQUARE ROOT, THE DIGITS ESTABLISHED IN THE SAID ONE OF THE PLURALITY OF MULTIPLE-ORDER DIGIT REPRESENTATIONS IN THE NEXT HIGHER-ORDER CIRCUIT WHEN SAID FIRST OUTPUT OF THE NEXT HIGHER-ORDER CIRCUIT ASSUMES A FIRST VALUE AND SAID SECOND OUTPUT OF THE NEXT HIGHER-ORDER CIRCUIT WHEN SAID FIRST OUTPUT OF THE NEXT HIGHER-ORDER CIRCUIT ASSUMES A SECOND VALUE, AND WHERE EACH DIGIT THUS ESTABLISHED IN SAID REMAINING PORTIONS IS ESTABLISHED IN THE ORDER THAT IS TWO GREATER THAN ITS CORRESPONDING ORDER IN SAID NEXT HIGHER-ORDER CIRCUIT; AND MEANS FOR ESTABLISHING, AS A SECOND OF THE PLURALITY OF MULTIPLE-ORDER DIGIT REPRESENTATIONS IN EACH CIRCUIT EXCEPT FOR THE CIRCUIT THAT CORRESPONDS TO THE MTH-ORDER OF THE SQUARE ROOT, A FUNCTION OF SAID FIRST OUTPUTS OF A HIGHER-ORDER CIRCUITS. 